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Microsoft puts Cobalt 200 VMs to work on chip design

Microsoft says Azure Cobalt 200 VMs are now handling electronic-design-automation workloads for its next chip generation, following internal tests spanning simulation, verification and timing.

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Nov 12, 2026 · 2 min read

Microsoft is using Azure Cobalt 200 virtual machines for electronic-design-automation workloads that support development of its next generation of Cobalt chips, the company said in a technical update on the deployment.

That puts Microsoft’s second-generation Arm-based cloud processor into the chip-design loop for its successor. Microsoft said existing Arm-enabled tools ran on Cobalt 200 without workflow changes, covering simulation, verification and signoff jobs that can run for days or spread across thousands of cores.

The evaluation covered Cadence Xcelium and Synopsys VCS for digital simulation, Cadence Spectre for analog and mixed-signal simulation, Siemens Calibre DRC for physical verification, and Synopsys PrimeTime for static timing analysis. Microsoft said its silicon-development environment handles hundreds of millions of EDA compute jobs each year, including physical-signoff runs that can use hundreds of gigabytes of memory for one design block.

The performance figures come from Microsoft’s internal tests and have not been independently reproduced. For the throughput tests, Microsoft configured each VM at its maximum available core count, ran multiple jobs concurrently and normalized throughput as jobs per hour per logical core. The Calibre test used a different measure, comparing wall time for a 16-core job on a quiet VM.

Microsoft reported that Cobalt 200 delivered 4.15 times Cobalt 100’s normalized per-logical-core throughput with Xcelium and 2.58 times with VCS. It also reported 1.38 times the prior generation’s throughput with Spectre, about 23% less wall time with Calibre, and 2.03 times the normalized peak per-logical-core throughput with PrimeTime. Microsoft said Cobalt 200 led the selected x86 Azure VMs in every test, but its post did not map the x86-A and x86-B chart labels to the named VM configurations.

The company attributed the results partly to full physical cores without simultaneous multithreading, 3 MB of dedicated L2 cache per core and high provisioned memory bandwidth. Its Cobalt 200 specifications list configurations with up to 128 virtual CPUs and 192 MB of system-level L3 cache.

Cadence separately said it had qualified native Cobalt 200 configurations for Xcelium Logic Simulation, Jasper Formal Platform, Innovus Implementation System and Tempus Timing Solution. Its qualification list does not include Spectre, which was part of Microsoft’s internal test set.

The companies did not publish power draw, energy use, cloud cost or performance-per-watt figures for the EDA tests. Microsoft also did not disclose the tested software versions, design inputs, storage configuration or complete VM tuning.

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