d-Matrix adopts NVIDIA NVLink Fusion for next-generation Raptor XPUs

NVIDIA said d-Matrix plans to connect its next-generation Raptor XPUs to NVIDIA’s rack-scale AI infrastructure platform through NVLink Fusion, extending the interconnect program to a specialized AI-inference chipmaker. NVIDIA’s blog post, published September 10, 2026, describes the integration as a planned deployment rather than a shipping product.

d-Matrix would join a growing list of NVLink Fusion adopters. NVIDIA said earlier this month that MediaTek agreed to a $3.5 billion NVIDIA investment in convertible bonds tied to adopting NVLink Fusion for custom AI accelerators.

If completed, the integration would let d-Matrix’s inference accelerators tap NVIDIA’s MGX rack-scale architecture. Under NVIDIA’s description of the NVLink Fusion program, they could potentially combine with NVIDIA GPUs, CPUs, networking, DPUs, and infrastructure-management software inside the same rack. NVIDIA is separately expanding that rack-scale footprint with cloud partners: AWS and NVIDIA plan to deploy two million additional NVIDIA GPUs across AWS infrastructure by 2028. The NVIDIA and d-Matrix announcements do not specify the NVLink generation, accelerator count, or rack topology planned for the d-Matrix implementation.

NVLink Fusion gives custom XPU and CPU designs access to NVLink through a bridge chiplet that uses a UCIe interface. Alongside NVLink Switches, that design lets non-NVIDIA silicon plug into the same high-speed fabric NVIDIA uses to link its own GPUs inside a rack.

“NVLink Fusion allows the hyperscalers or the custom ASIC designers to integrate their own custom CPU or XPU,” said Lie-Szu Juang, chair and chief strategy officer at GUC, describing the broader NVLink Fusion program rather than the d-Matrix integration specifically.

d-Matrix first detailed Raptor in November 2025 as a next-generation inference accelerator under development, saying it would use Andes Technology’s AndesCore AX46MPV RISC-V processor IP. The chip is also built around d-Matrix’s 3D stacked digital in-memory-compute technology, branded 3DIMC. The company has said it designed 3DIMC to reach roughly 10 times the memory bandwidth and 10 times the energy efficiency of HBM4. Those figures are d-Matrix’s own forward-looking targets rather than independently measured results.

d-Matrix says initial availability of Raptor XPUs integrated into NVIDIA MGX racks is expected in the fourth quarter of 2027. Neither company’s announcement names a customer or discloses commercial terms for the integration.